Modern microprocessors employ large on-chip random access memories (RAMs) in a variety of ways to enhance performance. These RAMs are typically static (SRAMs) due to associated speed advantages. The most common usage is in the form of on-chip caches. In many instances, such RAMs constitute the majority of transistors consumed on chip and are the largest occupants of chip area.
Embedded RAMs give rise to two particular problems during chip manufacturing. Because an embedded RAM occupies a significant portion of a chip""s area, the probability that a defect lies within the RAM is relatively high. The RAM thus becomes a controlling factor in chip yield. Second, the embedding of RAM not only makes its own testing difficult, but also impairs testability of all other functions on chip, such as the core logic. For example, much of the testing of other functions requires the use of the embedded RAM, which must be functioning properly.
Traditionally, semiconductor manufacturers have tackled RAM yield problems by incorporating a repair scheme with redundant rows and/or columns. For embedded RAM, however, this compounds the testing problems because a diagnosis to identify defects and the repair of those defects are required before the testing of core logic, for example, can begin.
Recently, Built-in Self -Test (BiST) and Built-in Self-Repair (BiSR) have been proposed as potential solutions to both of the above problems. The scheme presented by Koike et al, xe2x80x9cA 30 ns 64 Mb DRAM with Built-in Self-Test and Repair Functionxe2x80x9d, Int""l Solid State Circuits Conf., pp 150-151, February 1992, self-repairs only field failures. It employs traditional row-column repair to remove manufacturing defects. In the traditional method, a specialized RAM tester tests integrated circuit RAMs, and gathers and analyzes failure information, while the repair is done by blowing fuses. Koike""s on-chip scheme employs an on-chip microprogram read-only-memory (ROM) BiST scheme and self-repair logic block with a spare memory block.
The scheme presented by Chen and Sunada, xe2x80x9cDesign of a Self-testing and Self-repairing Structure for Highly Hierarchical Ultra Large Capacity Memory Chips,xe2x80x9d IEEE Trans. On VLSI Systems, pp. 88-97, Vol. 1, No. 2, June 1993, employs an on-chip RISC processor to collect and analyze a full failure bitmap to derive a repair solution. Besides the complexities of the RISC processor, the method also requires that a large enough block of the RAM under test must be available and fault-free to store a failure bitmap.
The BiST/BiSR schemes presented by Trueuer and Agarwal, xe2x80x9cBuilt-in Self-Diagnosis for Repairable Embedded RAMs,xe2x80x9d IEEE Design and Test of Computers, pp. 24-33, June 1993, and Bhavsar and Edmondson, xe2x80x9cTestability Strategy of the Alpha AXP 21164 Microprocessor,xe2x80x9d Int""l Test Conference, October 1994, are limited to self-repair with only spare rows.
The problem with the previous approaches here has been high complexity, e.g., the RISC processor of Chen and Sunada, or limited repair capability, e.g., using only spare rows or only spare columns. The present invention concerns a method for the self-repair of a RAM with both a spare row and a spare column using a significantly simpler built-in self-test/built-in self-repair (BiST/BiSR) logic. The scheme affords a greater flexibility in spare resource allocation and therefore can result in higher yield while utilizing simplified self-test/self-repair logic.
In accordance with a preferred embodiment of the present invention, a self-repair method for a random access memory (RAM) array comprises:
writing a value to the memory array;
reading a value from the memory array and comparing the read and write values to identify faulty memory cells in the memory array;
comparing an address of a newly-discovered faulty memory cell to at least one address of at least one previously-discovered faulty memory cell;
storing the address of the newly discovered faulty memory cell, if a column or row address of the newly-discovered faulty cell does not match any column or row address, respectively, of a previously-discovered faulty memory cell; and
setting flags to indicate that a spare row or a spare column must replace the row or column, respectively, identified by the address of the previously-discovered faulty memory cell, based on a present state of the flags and whether the row and/or column address of the newly-discovered memory cell matches the respective row and/or column address of one or more previously-discovered faulty memory cells.
The present state of the flags includes the present state of row and column xe2x80x9cmustxe2x80x9d flags, and entry valid flags.
Preferably, spare rows and column slices are allocated to replace faulty rows and columns respectively as indicated by the flags. Any remaining spare rows and columns, the addresses of which have been stored, are then allocated. Furthermore, the RAM is flagged as unrepairable if an insufficient number of spare rows or columns remain to replace all of the rows or columns containing faulty cells.
The preferred embodiment comprises a plurality of memory blocks, each block comprising a plurality of memory cells organized into rows and N-bit wide column slices, where N is 1 or greater. Each slice represents one bit of the addressed word. A portion of the address is used to select a row. Another portion is used to select a particular column within each column slice. A spare row and column slice are available to replace a row or column slice having a faulty cell. In storing spare column slice allocation information, it is preferable to use a unique column slice address, or identifier, to identify the replaced column slice. Note that, while in the preferred embodiment a spare column slice, rather than an individual spare column, is available to replace an entire column slice having a faulty cell, the concept is the same as for individual column replacement, and the present invention applies equally well to such a system. In this case, the terms column slice address and column address are synonymous. In general, however, we use column, or column slice address (or identifier) to identify the group (individual, complete slice, or otherwise) of columns being replaced.
A test and repair logic circuit locates faulty cells within the memory array. A failure bitmap has at least two entries, where each entry comprises a row address field and a column address field for storing the row and column slice address of a faulty cell detected by the test and repair logic circuit. In addition, each entry comprises a flag for indicating that the row indicated in the row address field must be replaced with a spare row. Similarly, each entry comprises a flag for indicating that the column indicated in the column address field must be replaced with a spare column. In a 2-entry failure bitmap, this signifies that at least two faulty cells are present in the indicated row or column. A spare allocation logic circuit uses the failure bitmap""s contents to decide how to allocate the spare rows and spare columns.
A segment allocation map comprising row-column repair registers and logic is maintained in which spare row and column allocation information generated after the self-test by the failure bitmap and spare allocation logic is stored. Alternately, if allocation information has previously been programmed into an array of fuse links during manufacture, the allocation information is read from the fuse array, and the segment allocation map configured accordingly.
Finally, the preferred embodiment, further comprises a column identifier encoder for encoding column identifiers of columns having faulty cells. A storage means is provided for storing encoded column identifiers and row identifiers. Such storage means includes, but is not limited to, a fuse array, a failure bitmap, or off-chip storage, such as may exist within a test system. Such storage means is also intended to encompass identifiers that are not physically stored but are determined, possibly on the fly, by the test system and down-loaded to the chip.
The repair engine of the preferred embodiment comprises a decoder for decoding an encoded identifier. The decoder itself comprises a counter which cycles through at least all of the allowed encoded identifier values. A comparator compares the counter""s value with a stored encoded identifier. The comparator""s output indicates whether there is a match. A validity check circuit determines whether the counter""s value is a valid encoded identifier, and provides an indication of the validity. When an encoded identifier is valid, the comparator output is sent to the spare allocation logic circuit, preferably by shifting it out over a serial line.